diff options
author | York Sun <york.sun@nxp.com> | 2016-12-28 08:43:43 -0800 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2017-01-04 19:40:46 -0500 |
commit | 63659ff317c72ff6d74a3147ad758c5904b034bc (patch) | |
tree | f5fa8fa262234608ae92150e32d5058d6d569dac /arch/powerpc/cpu | |
parent | c01e4a1a6f4ff8cbfa1fcdf984903e746cca3f66 (diff) | |
download | u-boot-imx-63659ff317c72ff6d74a3147ad758c5904b034bc.zip u-boot-imx-63659ff317c72ff6d74a3147ad758c5904b034bc.tar.gz u-boot-imx-63659ff317c72ff6d74a3147ad758c5904b034bc.tar.bz2 |
powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
Use Kconfig to select errata workaround.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 317 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 |
3 files changed, 319 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 0a4fa42..4878eed 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -331,6 +331,16 @@ config ARCH_B4420 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A005871 + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006384 + select SYS_FSL_ERRATUM_A006475 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007075 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -340,6 +350,16 @@ config ARCH_B4860 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A005871 + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006384 + select SYS_FSL_ERRATUM_A006475 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007075 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -348,6 +368,8 @@ config ARCH_B4860 config ARCH_BSC9131 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -357,7 +379,12 @@ config ARCH_BSC9131 config ARCH_BSC9132 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_A005434 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_IFC_A002769 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -367,6 +394,7 @@ config ARCH_BSC9132 config ARCH_C29X bool select FSL_LAW + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -377,6 +405,8 @@ config ARCH_C29X config ARCH_MPC8536 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -400,6 +430,7 @@ config ARCH_MPC8541 config ARCH_MPC8544 bool select FSL_LAW + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -409,6 +440,11 @@ config ARCH_MPC8544 config ARCH_MPC8548 bool select FSL_LAW + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_NMG_DDR120 + select SYS_FSL_ERRATUM_NMG_LBC103 + select SYS_FSL_ERRATUM_NMG_ETSEC129 + select SYS_FSL_ERRATUM_I2C_A004447 select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_SEC @@ -440,6 +476,8 @@ config ARCH_MPC8568 config ARCH_MPC8569 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -448,6 +486,10 @@ config ARCH_MPC8569 config ARCH_MPC8572 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_DDR_115 + select SYS_FSL_ERRATUM_DDR111_DDR134 select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -458,7 +500,17 @@ config ARCH_MPC8572 config ARCH_P1010 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_A007075 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_IFC_A002769 + select SYS_FSL_ERRATUM_P1010_A003549 + select SYS_FSL_ERRATUM_SEC_A003571 + select SYS_FSL_ERRATUM_IFC_A003399 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -468,6 +520,9 @@ config ARCH_P1010 config ARCH_P1011 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -478,6 +533,9 @@ config ARCH_P1011 config ARCH_P1020 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -488,6 +546,9 @@ config ARCH_P1020 config ARCH_P1021 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -498,7 +559,12 @@ config ARCH_P1021 config ARCH_P1022 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_SATA_A001 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -508,6 +574,9 @@ config ARCH_P1022 config ARCH_P1023 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_I2C_A004447 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -516,6 +585,9 @@ config ARCH_P1023 config ARCH_P1024 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -526,6 +598,9 @@ config ARCH_P1024 config ARCH_P1025 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -536,6 +611,9 @@ config ARCH_P1025 config ARCH_P2020 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_ESDHC_A001 select SYS_FSL_HAS_DDR3 @@ -548,7 +626,17 @@ config ARCH_P2041 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_CPU_A003999 + select SYS_FSL_ERRATUM_DDR_A003 + select SYS_FSL_ERRATUM_DDR_A003474 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_NMG_CPU_A011 + select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -558,7 +646,18 @@ config ARCH_P3041 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A005812 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_CPU_A003999 + select SYS_FSL_ERRATUM_DDR_A003 + select SYS_FSL_ERRATUM_DDR_A003474 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_NMG_CPU_A011 + select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -568,9 +667,29 @@ config ARCH_P4080 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004580 + select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A005812 + select SYS_FSL_ERRATUM_A007075 + select SYS_FSL_ERRATUM_CPC_A002 + select SYS_FSL_ERRATUM_CPC_A003 + select SYS_FSL_ERRATUM_CPU_A003999 + select SYS_FSL_ERRATUM_DDR_A003 + select SYS_FSL_ERRATUM_DDR_A003474 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_ESDHC13 select SYS_FSL_ERRATUM_ESDHC135 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_NMG_CPU_A011 + select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_P4080_ERRATUM_CPU22 + select SYS_P4080_ERRATUM_PCIE_A003 + select SYS_P4080_ERRATUM_SERDES8 + select SYS_P4080_ERRATUM_SERDES9 + select SYS_P4080_ERRATUM_SERDES_A001 + select SYS_P4080_ERRATUM_SERDES_A005 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -580,7 +699,14 @@ config ARCH_P5020 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_DDR_A003 + select SYS_FSL_ERRATUM_DDR_A003474 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -590,7 +716,14 @@ config ARCH_P5040 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004699 + select SYS_FSL_ERRATUM_A005812 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_DDR_A003 + select SYS_FSL_ERRATUM_DDR_A003474 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -603,6 +736,9 @@ config ARCH_T1023 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 @@ -614,6 +750,9 @@ config ARCH_T1024 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 @@ -625,6 +764,10 @@ config ARCH_T1040 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A008044 + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 @@ -636,6 +779,10 @@ config ARCH_T1042 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A008044 + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 @@ -647,6 +794,11 @@ config ARCH_T2080 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -657,6 +809,11 @@ config ARCH_T2081 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -667,6 +824,13 @@ config ARCH_T4160 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004468 + select SYS_FSL_ERRATUM_A005871 + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007798 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -676,6 +840,14 @@ config ARCH_T4240 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004468 + select SYS_FSL_ERRATUM_A005871 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007798 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -787,6 +959,151 @@ config SYS_CCSRBAR_DEFAULT if changed by pre-boot regime. The value here must match the current value in SoC. If not sure, do not change. +config SYS_FSL_ERRATUM_A004468 + bool + +config SYS_FSL_ERRATUM_A004477 + bool + +config SYS_FSL_ERRATUM_A004508 + bool + +config SYS_FSL_ERRATUM_A004580 + bool + +config SYS_FSL_ERRATUM_A004699 + bool + +config SYS_FSL_ERRATUM_A004849 + bool + +config SYS_FSL_ERRATUM_A004510 + bool + +config SYS_FSL_ERRATUM_A004510_SVR_REV + hex + depends on SYS_FSL_ERRATUM_A004510 + default 0x20 if ARCH_P4080 + default 0x10 + +config SYS_FSL_ERRATUM_A004510_SVR_REV2 + hex + depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) + default 0x11 + +config SYS_FSL_ERRATUM_A005125 + bool + +config SYS_FSL_ERRATUM_A005434 + bool + +config SYS_FSL_ERRATUM_A005812 + bool + +config SYS_FSL_ERRATUM_A005871 + bool + +config SYS_FSL_ERRATUM_A006261 + bool + +config SYS_FSL_ERRATUM_A006379 + bool + +config SYS_FSL_ERRATUM_A006384 + bool + +config SYS_FSL_ERRATUM_A006475 + bool + +config SYS_FSL_ERRATUM_A006593 + bool + +config SYS_FSL_ERRATUM_A007075 + bool + +config SYS_FSL_ERRATUM_A007186 + bool + +config SYS_FSL_ERRATUM_A007212 + bool + +config SYS_FSL_ERRATUM_A007798 + bool + +config SYS_FSL_ERRATUM_A008044 + bool + +config SYS_FSL_ERRATUM_CPC_A002 + bool + +config SYS_FSL_ERRATUM_CPC_A003 + bool + +config SYS_FSL_ERRATUM_CPU_A003999 + bool + +config SYS_FSL_ERRATUM_ELBC_A001 + bool + +config SYS_FSL_ERRATUM_I2C_A004447 + bool + +config SYS_FSL_A004447_SVR_REV + hex + depends on SYS_FSL_ERRATUM_I2C_A004447 + default 0x00 if ARCH_MPC8548 + default 0x10 if ARCH_P1010 + default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 + default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 + +config SYS_FSL_ERRATUM_IFC_A002769 + bool + +config SYS_FSL_ERRATUM_IFC_A003399 + bool + +config SYS_FSL_ERRATUM_NMG_CPU_A011 + bool + +config SYS_FSL_ERRATUM_NMG_ETSEC129 + bool + +config SYS_FSL_ERRATUM_NMG_LBC103 + bool + +config SYS_FSL_ERRATUM_P1010_A003549 + bool + +config SYS_FSL_ERRATUM_SATA_A001 + bool + +config SYS_FSL_ERRATUM_SEC_A003571 + bool + +config SYS_FSL_ERRATUM_SRIO_A004034 + bool + +config SYS_FSL_ERRATUM_USB14 + bool + +config SYS_P4080_ERRATUM_CPU22 + bool + +config SYS_P4080_ERRATUM_PCIE_A003 + bool + +config SYS_P4080_ERRATUM_SERDES8 + bool + +config SYS_P4080_ERRATUM_SERDES9 + bool + +config SYS_P4080_ERRATUM_SERDES_A001 + bool + +config SYS_P4080_ERRATUM_SERDES_A005 + bool + config SYS_FSL_NUM_LAWS int "Number of local access windows" depends on FSL_LAW diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 402a1ff..54b5b33 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -136,7 +136,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif __maybe_unused u32 svr = get_svr(); -#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001) if (IS_SVR_REV(svr, 1, 0)) { switch (SVR_SOC_VER(svr)) { case SVR_P1013: diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index d1b6699..4dff5c8 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -975,7 +975,7 @@ int cpu_init_r(void) #endif #endif -#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001) /* * For P1022/1013 Rev1.0 silicon, after power on SATA host * controller is configured in legacy mode instead of the |