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| author | Andy Fleming <afleming@freescale.com> | 2012-10-22 17:28:18 -0500 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 17:28:18 -0500 |
| commit | 23028d69e950023a3cb605751dbcb1e314be8b36 (patch) | |
| tree | 7d5f3869a4b585f6b3029e8c714af8ddecb932f4 /arch/powerpc/cpu | |
| parent | 19e4a00965f03d5d64af00b7b4258dff43e57d17 (diff) | |
| download | u-boot-imx-23028d69e950023a3cb605751dbcb1e314be8b36.zip u-boot-imx-23028d69e950023a3cb605751dbcb1e314be8b36.tar.gz u-boot-imx-23028d69e950023a3cb605751dbcb1e314be8b36.tar.bz2 | |
85xx: Protect timeout_save variable with ifdefs
The timeout_save variable was only used by the DDR111_134
erratum code. It was being set, but never used. Newer compilers
will actually complain about this.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 21840bf..f118dd5 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -22,8 +22,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, volatile ccsr_ddr_t *ddr; u32 temp_sdram_cfg; u32 total_gb_size_per_controller; - int timeout, timeout_save; + int timeout; #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + int timeout_save; volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; int csn = -1; @@ -305,7 +306,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, >> SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / (get_ddr_freq(0) >> 20)) << 1; +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 timeout_save = timeout; +#endif total_gb_size_per_controller >>= 4; /* shift down to gb size */ debug("total %d GB\n", total_gb_size_per_controller); debug("Need to wait up to %d * 10ms\n", timeout); |