summaryrefslogtreecommitdiff
path: root/arch/powerpc/cpu
diff options
context:
space:
mode:
authorYork Sun <yorksun@freescale.com>2011-03-02 14:24:11 -0800
committerKumar Gala <galak@kernel.crashing.org>2011-03-05 10:13:50 -0600
commitf5b6fb7c1b988cdec8db9e96dd05d1df46c22e6b (patch)
tree8d9bac65135dedd1eb7c02308a1922057747aa32 /arch/powerpc/cpu
parent8e29ebabf825ee0c85cb0c93d6aa495cc54811ab (diff)
downloadu-boot-imx-f5b6fb7c1b988cdec8db9e96dd05d1df46c22e6b.zip
u-boot-imx-f5b6fb7c1b988cdec8db9e96dd05d1df46c22e6b.tar.gz
u-boot-imx-f5b6fb7c1b988cdec8db9e96dd05d1df46c22e6b.tar.bz2
powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c20
1 files changed, 14 insertions, 6 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 936c195..8ef6ca8 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -333,6 +333,9 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
unsigned char acttoact_mclk;
/* Last write data pair to read command issue interval (tWTR) */
unsigned char wrtord_mclk;
+ /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
+ static const u8 wrrec_table[] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
@@ -371,6 +374,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
+
+ wrrec_mclk = wrrec_table[wrrec_mclk - 1];
if (popts->OTF_burst_chop_en)
wrrec_mclk += 2;
@@ -810,6 +815,12 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
unsigned int bl; /* BL: Burst Length */
unsigned int wr_mclk;
+ /*
+ * DDR_SDRAM_MODE doesn't support 9,11,13,15
+ * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
+ * for this table
+ */
+ static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
const unsigned int mclk_ps = get_memory_clk_period_ps();
int i;
@@ -853,13 +864,10 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
* 1=fast exit DLL on (tXP)
*/
dll_on = 1;
+
wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
- if (wr_mclk >= 12)
- wr = 6;
- else if (wr_mclk >= 9)
- wr = 5;
- else
- wr = wr_mclk - 4;
+ wr = wr_table[wr_mclk - 5];
+
dll_rst = 0; /* dll no reset */
mode = 0; /* normal mode */