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authorCodrin Ciubotariu <codrin.ciubotariu@freescale.com>2015-01-12 14:08:31 +0200
committerYork Sun <yorksun@freescale.com>2015-01-16 09:32:26 -0800
commitc2a61cd232910cb5c53d67699394dcc29e96fab8 (patch)
treea669a933b95519d843a098ee7824b67c914f5db0 /arch/powerpc/cpu
parent7d33a87d9ddb7a862a12c50d1c83a2f7853cc1bf (diff)
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arch/powerpc: Add SGMII support for the L2 Switch ports
Some Freescale SoCs like T1020 and T1040 have an integrated L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs over SGMII and QSGMII. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c6
-rw-r--r--arch/powerpc/cpu/mpc85xx/t1040_serdes.c8
2 files changed, 10 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index c7d9622..acb1353 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -78,6 +78,12 @@ static const char *serdes_prtcl_str[] = {
[INTERLAKEN] = "INTERLAKEN",
[QSGMII_SW1_A] = "QSGMII_SW1_A",
[QSGMII_SW1_B] = "QSGMII_SW1_B",
+ [SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
+ [SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
+ [SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
+ [SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
+ [SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
+ [SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
};
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
index d86bb27..d5dccd5 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
@@ -33,10 +33,10 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
- [0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
- PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
- [0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
- PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
+ [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
+ PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
+ [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
+ PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,