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authorRoy Zang <tie-fei.zang@freescale.com>2011-01-07 00:24:27 -0600
committerKumar Gala <galak@kernel.crashing.org>2011-01-14 01:32:22 -0600
commitae026ffd1e1a3f98b13c121acf5a677a5925a0e1 (patch)
tree07042933aab306f9686495de4af8e1cca26f4c67 /arch/powerpc/cpu
parent3b4456ec391877a950dd5e98ee20df6560f0e1af (diff)
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fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)
False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c8
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index d5c34c8..4e2cb4a 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -56,6 +56,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
puts("Work-around for Erratum ESDHC135 enabled\n");
#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
+ puts("Work-around for Erratum ESDHC136 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 1d016c4..354b222 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -394,6 +394,14 @@ int cpu_init_r(void)
setup_mp();
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+ {
+ void *p;
+ p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+ setbits_be32(p, 1 << (31 - 14));
+ }
+#endif
+
#ifdef CONFIG_SYS_LBC_LCRR
/*
* Modify the CLKDIV field of LCRR register to improve the writing