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| author | Joakim Tjernlund <joakim.tjernlund@transmode.se> | 2012-07-23 10:58:02 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-08-22 16:07:42 -0500 |
| commit | 89f4289958c12e6b64a6073f820255c1f719c5cc (patch) | |
| tree | 1ee3edbe1f1f2f23e6276420082232c02f6b2c9c /arch/powerpc/cpu | |
| parent | e66443fdb5355e68cfdbbdd37248c4b7eb4968f5 (diff) | |
| download | u-boot-imx-89f4289958c12e6b64a6073f820255c1f719c5cc.zip u-boot-imx-89f4289958c12e6b64a6073f820255c1f719c5cc.tar.gz u-boot-imx-89f4289958c12e6b64a6073f820255c1f719c5cc.tar.bz2 | |
mpc85xx: Initial SP alignment is wrong.
PowerPC mandates SP to be 16 bytes aligned.
Furthermore, a stack frame is added, pointing to the reset vector
which may in the way when gdb is walking the stack because
the reset vector may not accessible depending on emulator settings.
Also use a temp register so gdb doesn't pick up intermediate values.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 6aabc30..b1998b2 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -855,18 +855,12 @@ version_string: .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ - lis r1,CONFIG_SYS_INIT_RAM_ADDR@h - ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l - + lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ li r0,0 - stwu r0,-4(r1) - stwu r0,-4(r1) /* Terminate call chain */ - - stwu r1,-8(r1) /* Save back chain and move SP */ - lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0,RESET_VECTOR@l - stwu r1,-8(r1) /* Save back chain and move SP */ - stw r0,+12(r1) /* Save return addr (underflow vect) */ + stw r0,0(r3) /* Terminate Back Chain */ + stw r0,+4(r3) /* NULL return address. */ + mr r1,r3 /* Transfer to SP(r1) */ GET_GOT bl cpu_init_early_f |