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| author | Stefan Roese <sr@denx.de> | 2010-11-26 15:45:34 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-11-28 11:07:37 +0100 |
| commit | 7920954bd2bd9d49013378a722fb2325cbbeadeb (patch) | |
| tree | f298231dc2ba65efd1ed8e4dcc71458e277d1ab5 /arch/powerpc/cpu/ppc4xx | |
| parent | 28e94bb2f7b796f58587752ab018b7d23fdc9061 (diff) | |
| download | u-boot-imx-7920954bd2bd9d49013378a722fb2325cbbeadeb.zip u-boot-imx-7920954bd2bd9d49013378a722fb2325cbbeadeb.tar.gz u-boot-imx-7920954bd2bd9d49013378a722fb2325cbbeadeb.tar.bz2 | |
ppc4xx: Flush complete dcache in relocate_code()
When the cache is enabled in SDRAM we need to flush not only the global
data area but also the bd_info struct in relocate_code. This patch now
flushed the complete dcache (all dcache lines) via flush_dcache() instead
of adding a flush_dcache_range() call for bd_info since this is faster.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/start.S | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 65195f5..0e75794 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1389,8 +1389,8 @@ in32r: relocate_code: #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) /* - * We need to flush the initial global data (gd_t) before the dcache - * will be invalidated. + * We need to flush the initial global data (gd_t) and bd_info + * before the dcache will be invalidated. */ /* Save registers */ @@ -1398,10 +1398,11 @@ relocate_code: mr r10, r4 mr r11, r5 - /* Flush initial global data range */ - mr r3, r4 - addi r4, r4, GENERATED_GBL_DATA_SIZE@l - bl flush_dcache_range + /* + * Flush complete dcache, this is faster than flushing the + * ranges for global_data and bd_info instead. + */ + bl flush_dcache #if defined(CONFIG_SYS_INIT_DCACHE_CS) /* |