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authorStefan Roese <sr@denx.de>2010-11-26 15:45:22 +0100
committerStefan Roese <sr@denx.de>2010-11-28 11:06:47 +0100
commit28e94bb2f7b796f58587752ab018b7d23fdc9061 (patch)
treed753ad2372c254ea98e9c53ddc97fbe0a429e7ea /arch/powerpc/cpu/ppc4xx
parent844f07d8a1f1330c97631b23fbf6425db2dc1508 (diff)
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ppc4xx/POST: Handle cached SDRAM correctly in Denali (440EPx) ECC POST
This patch fixes a problem in the Denali (440EPx) SDRAM ECC POST test. When cache is enabled in the SDRAM area, the values written to SDRAM need to be flushed from cache to SDRAM using the dcfb instruction. Without this patch the POST ECC test failed. Now its working again on platforms with cache enabled in SDRAM. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx')
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