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authorWolfgang Denk <wd@denx.de>2010-07-24 20:34:13 +0200
committerWolfgang Denk <wd@denx.de>2010-07-24 20:34:13 +0200
commit96623171423a94092cde80642328fda58a92c894 (patch)
treee5e98dc33dc17399ad16d85d6df1c36d44e22889 /arch/powerpc/cpu/ppc4xx/ecc.c
parent47ec10c5975f0ce8f4a748c7b76c45c0fb60c0ac (diff)
parent1ffcb86ce06a252ff6f4620691eb347c8ab47b61 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx/ecc.c')
-rw-r--r--arch/powerpc/cpu/ppc4xx/ecc.c21
1 files changed, 20 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c
index f105605..49f28d9 100644
--- a/arch/powerpc/cpu/ppc4xx/ecc.c
+++ b/arch/powerpc/cpu/ppc4xx/ecc.c
@@ -130,7 +130,26 @@ static void program_ecc_addr(unsigned long start_address,
/* clear ECC error repoting registers */
mtsdram(SDRAM_ECCES, 0xffffffff);
- mtdcr(0x4c, 0xffffffff);
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
+ /*
+ * IBM DDR(1) core (440GX):
+ * Clear Mx bits in SDRAM0_BESR0/1
+ */
+ mtsdram(SDRAM0_BESR0, 0xffffffff);
+ mtsdram(SDRAM0_BESR1, 0xffffffff);
+#elif defined(CONFIG_440)
+ /*
+ * 440/460 DDR2 core:
+ * Clear EMID (Error PLB Master ID) in MQ0_ESL
+ */
+ mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
+#else
+ /*
+ * 405EX(r) DDR2 core:
+ * Clear M0ID (Error PLB Master ID) in SDRAM_BESR
+ */
+ mtsdram(SDRAM_BESR, 0xf0000000);
+#endif
mtsdram(SDRAM_MCOPT1,
(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);