powerpc/mpc85xx: Add T4240 SoC

Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

2 files changed, 18 insertions, 5 deletions

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index fb78784..4d96d1b 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -75,6 +75,8 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(P5020, P5020, 2),
 	CPU_TYPE_ENTRY(P5021, P5021, 2),
 	CPU_TYPE_ENTRY(P5040, P5040, 4),
+	CPU_TYPE_ENTRY(T4240, T4240, 0),
+	CPU_TYPE_ENTRY(T4120, T4120, 0),
 	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 #elif defined(CONFIG_MPC86xx)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e7ff59a..d4f8ece 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -34,8 +34,13 @@
 #define SRIO_LCSBA1CSR 0x60000000
 
 #if defined(CONFIG_FSL_CORENET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
+	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
+#else
 	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
 	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
+#endif
 	#define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
 	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC85xx)
@@ -236,7 +241,13 @@ void srio_init(void)
 {
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
 	int srio1_used = 0, srio2_used = 0;
+	u32 *devdisr;
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	devdisr = &gur->devdisr3;
+#else
+	devdisr = &gur->devdisr;
+#endif
 	if (is_serdes_configured(SRIO1)) {
 		set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
 				law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
@@ -273,16 +284,16 @@ void srio_init(void)
 #ifdef CONFIG_FSL_CORENET
 	/* On FSL_CORENET devices we can disable individual ports */
 	if (!srio1_used)
-		setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
+		setbits_be32(devdisr, _DEVDISR_SRIO1);
 	if (!srio2_used)
-		setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
+		setbits_be32(devdisr, _DEVDISR_SRIO2);
 #endif
 
 	/* neither port is used - disable everything */
 	if (!srio1_used && !srio2_used) {
-		setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
-		setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
-		setbits_be32(&gur->devdisr, _DEVDISR_RMU);
+		setbits_be32(devdisr, _DEVDISR_SRIO1);
+		setbits_be32(devdisr, _DEVDISR_SRIO2);
+		setbits_be32(devdisr, _DEVDISR_RMU);
 	}
 }