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author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2011-07-07 20:36:47 +0530 |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2011-09-29 19:01:04 -0500 |
commit | bc6bbd6be85973359e89f53e3bfbba2a3549da09 (patch) | |
tree | 6e898ab4aa36d24354c9d3a186eb7048def0e3ec /arch/powerpc/cpu/mpc8xxx | |
parent | fb855f43a1cdcda5f93d971063330505548d5919 (diff) | |
download | u-boot-imx-bc6bbd6be85973359e89f53e3bfbba2a3549da09.zip u-boot-imx-bc6bbd6be85973359e89f53e3bfbba2a3549da09.tar.gz u-boot-imx-bc6bbd6be85973359e89f53e3bfbba2a3549da09.tar.bz2 |
fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.
Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.
Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx')
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c index e794821..6682496 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -43,10 +43,12 @@ void init_early_memctl_regs(void) set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); +#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT) set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); #endif +#endif #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); |