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author | Tom Rini <trini@ti.com> | 2013-05-14 18:47:43 -0400 |
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committer | Tom Rini <trini@ti.com> | 2013-05-15 08:41:04 -0400 |
commit | fb651b10d43be36e7d7e16704c4b5ea1e295587a (patch) | |
tree | b2f5450c8031935a92d0357cb677bac99d3be537 /arch/powerpc/cpu/mpc8xxx | |
parent | d6ed3222229974682799bd2083f2ceeac6f912b1 (diff) | |
parent | f63d638dad5dd13f445d1e87ce824d4a7cd61f79 (diff) | |
download | u-boot-imx-fb651b10d43be36e7d7e16704c4b5ea1e295587a.zip u-boot-imx-fb651b10d43be36e7d7e16704c4b5ea1e295587a.tar.gz u-boot-imx-fb651b10d43be36e7d7e16704c4b5ea1e295587a.tar.bz2 |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx')
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/cpu.c | 1 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/main.c | 26 |
2 files changed, 18 insertions, 9 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 39525fb..0087cd0 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -77,6 +77,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(P5040, P5040, 4), CPU_TYPE_ENTRY(T4240, T4240, 0), CPU_TYPE_ENTRY(T4120, T4120, 0), + CPU_TYPE_ENTRY(T4160, T4160, 0), CPU_TYPE_ENTRY(B4860, B4860, 0), CPU_TYPE_ENTRY(G4860, G4860, 0), CPU_TYPE_ENTRY(G4060, G4060, 0), diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 5311a26..7a8636d 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -186,7 +186,7 @@ const char * step_to_string(unsigned int step) { return step_string_tbl[s]; } -unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, +static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, unsigned int dbw_cap_adj[]) { int i, j; @@ -354,6 +354,11 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, return total_mem; } +/* Use weak function to allow board file to override the address assignment */ +__attribute__((weak, alias("__step_assign_addresses"))) +unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, + unsigned int dbw_cap_adj[]); + unsigned long long fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only) @@ -541,14 +546,17 @@ phys_size_t fsl_ddr_sdram(void) total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); /* setup 3-way interleaving before enabling DDRC */ - switch (info.memctl_opts[0].memctl_interleaving_mode) { - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode); - break; - default: - break; + if (info.memctl_opts[0].memctl_interleaving) { + switch (info.memctl_opts[0].memctl_interleaving_mode) { + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + fsl_ddr_set_intl3r( + info.memctl_opts[0].memctl_interleaving_mode); + break; + default: + break; + } } /* Program configuration registers. */ |