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authorYork Sun <yorksun@freescale.com>2013-03-25 07:40:07 +0000
committerAndy Fleming <afleming@freescale.com>2013-05-24 16:54:11 -0500
commitf69814397e7efaf0b2bfa3c83425c906ce6b50f4 (patch)
tree3526ce4f78bb8d70ad0e0b80df23002a5ee5fb07 /arch/powerpc/cpu/mpc8xxx
parent5f208d118a8590843aaca723d304b35f2729c141 (diff)
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powerpc/chassis2: Change core numbering scheme
To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx')
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c53
1 files changed, 44 insertions, 9 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 23e008e..bc26855 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -103,35 +103,70 @@ static struct cpu_type cpu_type_list[] = {
};
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+static inline u32 init_type(u32 cluster, int init_id)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
+ u32 type = in_be32(&gur->tp_ityp[idx]);
+
+ if (type & TP_ITYP_AV)
+ return type;
+
+ return 0;
+}
+
u32 compute_ppc_cpumask(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int i = 0, count = 0;
- u32 cluster, mask = 0;
+ u32 cluster, type, mask = 0;
do {
int j;
- cluster = in_be32(&gur->tp_cluster[i++].lower);
- for (j = 0; j < 4; j++) {
- u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
- u32 type = in_be32(&gur->tp_ityp[idx]);
-
- if (type & TP_ITYP_AV) {
+ cluster = in_be32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ type = init_type(cluster, j);
+ if (type) {
if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
mask |= 1 << count;
+ count++;
}
- count++;
}
+ i++;
} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
return mask;
}
+
+int fsl_qoriq_core_to_cluster(unsigned int core)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int i = 0, count = 0;
+ u32 cluster;
+
+ do {
+ int j;
+ cluster = in_be32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ if (init_type(cluster, j)) {
+ if (count == core)
+ return i;
+ count++;
+ }
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+ return -1; /* cannot identify the cluster */
+}
+
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
/*
* Before chassis genenration 2, the cpumask should be hard-coded.
* In case of cpu type unknown or cpumask unset, use 1 as fail save.
*/
#define compute_ppc_cpumask() 1
+#define fsl_qoriq_core_to_cluster(x) x
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);