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authorJames Yang <James.Yang@freescale.com>2013-07-22 09:35:26 -0700
committerYork Sun <yorksun@freescale.com>2013-08-09 12:43:32 -0700
commitc45f5c08b7130b76c3f33fab41f92ebdd4a54108 (patch)
treeeb9632bfda927d84f6d437591f5b7ac8c11624a1 /arch/powerpc/cpu/mpc8xxx
parenta8d9758d0162f2eb8589be9d60b833241f043c6d (diff)
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powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]
The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but the mask omitted the LSB. This patch provides a 2-bit wide mask. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx')
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index bf5a6f2..242eb47 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -364,7 +364,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
ddr->timing_cfg_3 = (0
| ((ext_pretoact & 0x1) << 28)
- | ((ext_acttopre & 0x2) << 24)
+ | ((ext_acttopre & 0x3) << 24)
| ((ext_acttorw & 0x1) << 22)
| ((ext_refrec & 0x1F) << 16)
| ((ext_caslat & 0x3) << 12)