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authorYork Sun <yorksun@freescale.com>2012-10-08 07:44:25 +0000
committerAndy Fleming <afleming@freescale.com>2012-10-22 14:31:28 -0500
commiteb5394120643922626f18e5fe7b0b3dc0ed43b9a (patch)
tree968121a3577cf3c8e14bd435d9c8c303140f3cd1 /arch/powerpc/cpu/mpc8xxx
parentf31cfd19253713eea59311dec9e99df5d43b2db9 (diff)
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powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select the DDR controller target. However, the post-translation address will be presented to the selected DDR controller. It is possible that the pre- translation address selects one DDR controller but the post-translation address exists in a different DDR controller when using certain DDR controller interleaving modes. The device may fail to boot under these circumstances. Note that a DDR MSE error will not be detected since DDR controller bounds registers are programmed to be the same when configured for DDR controller interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx')
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/util.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
index afc5fae..940ffff 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
@@ -121,6 +121,16 @@ void fsl_ddr_set_intl3r(const unsigned int granule_size)
#endif
}
+u32 fsl_ddr_get_intl3r(void)
+{
+ u32 val = 0;
+#ifdef CONFIG_E6500
+ u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
+ val = *mcintl3r;
+#endif
+ return val;
+}
+
void board_add_ram_info(int use_default)
{
#if defined(CONFIG_MPC83xx)