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author | Wolfgang Denk <wd@denx.de> | 2011-01-25 21:13:04 +0100 |
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committer | Wolfgang Denk <wd@denx.de> | 2011-01-25 21:13:04 +0100 |
commit | 5aebe3b07254d9ec8f7ae23a4525a6c535a7f858 (patch) | |
tree | 398660b7a43c39cee91c51e54678eab46aa7103d /arch/powerpc/cpu/mpc8xxx/ddr/main.c | |
parent | d6a5e6d531e357dd8016141f73d370d02886a7eb (diff) | |
parent | 92966835e96af324fed574815036e481be807d04 (diff) | |
download | u-boot-imx-5aebe3b07254d9ec8f7ae23a4525a6c535a7f858.zip u-boot-imx-5aebe3b07254d9ec8f7ae23a4525a6c535a7f858.tar.gz u-boot-imx-5aebe3b07254d9ec8f7ae23a4525a6c535a7f858.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx/ddr/main.c')
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/main.c | 31 |
1 files changed, 26 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index e3888ff..bb96d66 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -233,7 +233,8 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, } unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only) { unsigned int i, j; unsigned int all_controllers_memctl_interleaving = 0; @@ -338,7 +339,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) &pinfo->memctl_opts[i], &ddr_reg[i], &timing_params[i], pinfo->dimm_params[i], - dbw_capacity_adjust[i]); + dbw_capacity_adjust[i], + size_only); } default: @@ -405,7 +407,7 @@ phys_size_t fsl_ddr_sdram(void) memset(&info, 0, sizeof(fsl_ddr_info_t)); /* Compute it once normally. */ - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD); + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); /* Check for memory controller interleaving. */ memctl_interleaved = 0; @@ -430,7 +432,8 @@ phys_size_t fsl_ddr_sdram(void) info.memctl_opts[i].memctl_interleaving = 0; debug("Recomputing with memctl_interleaving off.\n"); total_memory = fsl_ddr_compute(&info, - STEP_ASSIGN_ADDRESSES); + STEP_ASSIGN_ADDRESSES, + 0); } } @@ -478,3 +481,21 @@ phys_size_t fsl_ddr_sdram(void) return total_memory; } + +/* + * fsl_ddr_sdram_size() - This function only returns the size of the total + * memory without setting ddr control registers. + */ +phys_size_t +fsl_ddr_sdram_size(void) +{ + fsl_ddr_info_t info; + unsigned long long total_memory = 0; + + memset(&info, 0 , sizeof(fsl_ddr_info_t)); + + /* Compute it once normally. */ + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); + + return total_memory; +} |