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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:25 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:28 -0500 |
| commit | eb5394120643922626f18e5fe7b0b3dc0ed43b9a (patch) | |
| tree | 968121a3577cf3c8e14bd435d9c8c303140f3cd1 /arch/powerpc/cpu/mpc86xx | |
| parent | f31cfd19253713eea59311dec9e99df5d43b2db9 (diff) | |
| download | u-boot-imx-eb5394120643922626f18e5fe7b0b3dc0ed43b9a.zip u-boot-imx-eb5394120643922626f18e5fe7b0b3dc0ed43b9a.tar.gz u-boot-imx-eb5394120643922626f18e5fe7b0b3dc0ed43b9a.tar.bz2 | |
powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc86xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc86xx/fdt.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc86xx/mp.c | 9 |
2 files changed, 7 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 61f5110..2f955fe 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -20,7 +20,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP int off; - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c index 30c99eb..de705f0 100644 --- a/arch/powerpc/cpu/mpc86xx/mp.c +++ b/arch/powerpc/cpu/mpc86xx/mp.c @@ -90,8 +90,11 @@ int cpu_release(int nr, int argc, char * const argv[]) return 1; } -u32 determine_mp_bootpg(void) +u32 determine_mp_bootpg(unsigned int *pagesize) { + if (pagesize) + *pagesize = 4096; + /* if we have 4G or more of memory, put the boot page at 4Gb-1M */ if ((u64)gd->ram_size > 0xfffff000) return (0xfff00000); @@ -101,7 +104,7 @@ u32 determine_mp_bootpg(void) void cpu_mp_lmb_reserve(struct lmb *lmb) { - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); /* tell u-boot we stole a page */ lmb_reserve(lmb, bootpg, 4096); @@ -115,7 +118,7 @@ void setup_mp(void) { extern ulong __secondary_start_page; ulong fixup = (ulong)&__secondary_start_page; - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); u32 bootpg_va; if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) { |