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| author | York Sun <yorksun@freescale.com> | 2013-06-25 11:37:48 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:39 -0700 |
| commit | c63e137014cf148bc1d234128941dccee3d519ae (patch) | |
| tree | afb69c22c33459d14a174973083e2a70e5f49ea7 /arch/powerpc/cpu/mpc86xx | |
| parent | b61e06156660579ea6e248abd2506ebdd85e7a14 (diff) | |
| download | u-boot-imx-c63e137014cf148bc1d234128941dccee3d519ae.zip u-boot-imx-c63e137014cf148bc1d234128941dccee3d519ae.tar.gz u-boot-imx-c63e137014cf148bc1d234128941dccee3d519ae.tar.bz2 | |
powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc86xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc86xx/ddr-8641.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/arch/powerpc/cpu/mpc86xx/ddr-8641.c index 92ba26d..33a91f9 100644 --- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c +++ b/arch/powerpc/cpu/mpc86xx/ddr-8641.c @@ -15,7 +15,7 @@ #endif void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num) + unsigned int ctrl_num, int step) { unsigned int i; volatile ccsr_ddr_t *ddr; |