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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:22 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:26 -0500 |
| commit | 57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2 (patch) | |
| tree | 4bf4bebd73d19138e8f726112ba0c41cbde94a15 /arch/powerpc/cpu/mpc86xx/interrupts.c | |
| parent | 111fd19e3b9eb1005fd24ef09c163dd10103f5fa (diff) | |
| download | u-boot-imx-57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2.zip u-boot-imx-57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2.tar.gz u-boot-imx-57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2.tar.bz2 | |
powerpc/mpc8xxx: Update DDR registers
DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.
CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
000 -> Termsel off
001 -> 120 Ohm
010 -> 180 Ohm
011 -> 75 Ohm
100 -> 110 Ohm
101 -> 60 Ohm
110 -> 70 Ohm
111 -> 47 Ohm
Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.
Extend DDR register timing_cfg_1 to have 4 bits for each field.
DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc86xx/interrupts.c')
0 files changed, 0 insertions, 0 deletions