powerpc/mp: add support for discontiguous cores

Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more.  We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

3 files changed, 21 insertions, 22 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 22fa461..f51829e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -64,7 +64,8 @@ int checkcpu (void)
 	u32 ddr_ratio = 0;
 #endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
-	int i;
+	unsigned int i, core, nr_cores = cpu_numcores();
+	u32 mask = cpu_mask();
 
 	svr = get_svr();
 	major = SVR_MAJ(svr);
@@ -119,11 +120,11 @@ int checkcpu (void)
 	get_sys_info(&sysinfo);
 
 	puts("Clock Configuration:");
-	for (i = 0; i < cpu_numcores(); i++) {
+	for_each_cpu(i, core, nr_cores, mask) {
 		if (!(i & 3))
 			printf ("\n       ");
-		printf("CPU%d:%-4s MHz, ",
-				i,strmhz(buf1, sysinfo.freqProcessor[i]));
+		printf("CPU%d:%-4s MHz, ", core,
+			strmhz(buf1, sysinfo.freqProcessor[core]));
 	}
 	printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 758e6d7..ffc2a9a 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -221,14 +221,14 @@ ulong get_spin_virt_addr(void)
 #ifdef CONFIG_FSL_CORENET
 static void plat_mp_up(unsigned long bootpg)
 {
-	u32 up, cpu_up_mask, whoami;
+	u32 cpu_up_mask, whoami;
 	u32 *table = (u32 *)get_spin_virt_addr();
 	volatile ccsr_gur_t *gur;
 	volatile ccsr_local_t *ccm;
 	volatile ccsr_rcpm_t *rcpm;
 	volatile ccsr_pic_t *pic;
 	int timeout = 10;
-	u32 nr_cpus;
+	u32 mask = cpu_mask();
 	struct law_entry e;
 
 	gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -236,8 +236,6 @@ static void plat_mp_up(unsigned long bootpg)
 	rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 	pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 
-	nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
-
 	whoami = in_be32(&pic->whoami);
 	cpu_up_mask = 1 << whoami;
 	out_be32(&ccm->bstrl, bootpg);
@@ -251,19 +249,18 @@ static void plat_mp_up(unsigned long bootpg)
 	/* disable time base at the platform */
 	out_be32(&rcpm->ctbenrl, cpu_up_mask);
 
-	/* release the hounds */
-	up = ((1 << nr_cpus) - 1);
-	out_be32(&gur->brrl, up);
+	out_be32(&gur->brrl, mask);
 
 	/* wait for everyone */
 	while (timeout) {
-		int i;
-		for (i = 0; i < nr_cpus; i++) {
-			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
-				cpu_up_mask |= (1 << i);
-		};
+		unsigned int i, cpu, nr_cpus = cpu_numcores();
 
-		if ((cpu_up_mask & up) == up)
+		for_each_cpu(i, cpu, nr_cpus, mask) {
+			if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
+				cpu_up_mask |= (1 << cpu);
+		}
+
+		if ((cpu_up_mask & mask) == mask)
 			break;
 
 		udelay(100);
@@ -272,7 +269,7 @@ static void plat_mp_up(unsigned long bootpg)
 
 	if (timeout == 0)
 		printf("CPU up timeout. CPU up mask is %x should be %x\n",
-			cpu_up_mask, up);
+			cpu_up_mask, mask);
 
 	/* enable time base at the platform */
 	out_be32(&rcpm->ctbenrl, 0);
@@ -283,7 +280,7 @@ static void plat_mp_up(unsigned long bootpg)
 	mtspr(SPRN_TBWU, 0);
 	mtspr(SPRN_TBWL, 0);
 
-	out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
+	out_be32(&rcpm->ctbenrl, mask);
 
 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
 	/*
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index a83dfeb..ce47532 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -41,6 +41,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+	unsigned int cpu;
 
 	const u8 core_cplx_PLL[16] = {
 		[ 0] = 0,	/* CC1 PPL / 1 */
@@ -97,11 +98,11 @@ void get_sys_info (sys_info_t * sysInfo)
 			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
 	}
 	rcw_tmp = in_be32(&gur->rcwsr[3]);
-	for (i = 0; i < cpu_numcores(); i++) {
-		u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
+	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 
-		sysInfo->freqProcessor[i] =
+		sysInfo->freqProcessor[cpu] =
 			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
 	}