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| author | York Sun <yorksun@freescale.com> | 2013-09-16 12:49:31 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 16:15:17 -0700 |
| commit | 133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a (patch) | |
| tree | 8310923265a2fd56d900bc4b973cfbb2f95dfc75 /arch/powerpc/cpu/mpc85xx | |
| parent | e512c50bc9e3ef0bcf209620cabfc6ef35f22ff3 (diff) | |
| download | u-boot-imx-133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a.zip u-boot-imx-133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a.tar.gz u-boot-imx-133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a.tar.bz2 | |
powerpc/mpc85xx: Add workaround for erratum A006379
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.
Erratum A006379 applies to
T4240 rev 1.0
B4860 rev 1.0, 2.0
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 5 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index c441bd2..1e5a43f 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -7,6 +7,7 @@ #include <common.h> #include <command.h> #include <linux/compiler.h> +#include <asm/fsl_errata.h> #include <asm/processor.h> #include "fsl_corenet_serdes.h" @@ -245,6 +246,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) + puts("Work-around for Erratum A006379 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 if (IS_SVR_REV(svr, 1, 0)) puts("Work-around for Erratum A003571 enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index a8107a9..b31efb7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -19,6 +19,7 @@ #include <asm/io.h> #include <asm/cache.h> #include <asm/mmu.h> +#include <asm/fsl_errata.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> @@ -160,6 +161,12 @@ static void enable_cpc(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) { + setbits_be32(&cpc->cpchdbcr0, + CPC_HDBCR0_SPLRU_LEVEL_EN); + } +#endif out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ |