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authorEbony Zhu <b45385@freescale.com>2014-09-04 11:53:00 -0500
committerYork Sun <yorksun@freescale.com>2014-09-24 13:10:52 -0700
commit07c4eea4846cde938c4b0d8c1ddee95d373693ed (patch)
tree89f2755f76242093b164eb8861991eba9fb1c57b /arch/powerpc/cpu/mpc85xx
parent1de271b487d60c613568ad61fc005ff850f2ed71 (diff)
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powerpc/mpc85xx: Serdes protocol "00" is supported
"0x00" is a valid serdes protocol for QorIQ parts, and can not be used to test whether the serdes is enabled or disabled. Signed-off-by: Ebony Zhu <b45385@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index d1fc76a..8edf5bb 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -186,11 +186,6 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
#endif
cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
- /* Is serdes enabled at all? */
- if (!cfg) {
- printf("SERDES%d is not enabled\n", sd + 1);
- return 0;
- }
/* Erratum A-007186
* Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)