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| author | Wolfgang Denk <wd@denx.de> | 2011-07-30 01:39:14 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-07-30 01:39:14 +0200 |
| commit | dd620b26332eb1e9fc0216760909c4046ba09745 (patch) | |
| tree | dac488abee6a6768479629b2c1b2d904d0f9e309 /arch/powerpc/cpu/mpc85xx/start.S | |
| parent | 84b5e8022ef62b68df360392a55c4fc2f2e568d7 (diff) | |
| parent | 57567361769bfa02d0622c06e5e9f66392e2593a (diff) | |
| download | u-boot-imx-dd620b26332eb1e9fc0216760909c4046ba09745.zip u-boot-imx-dd620b26332eb1e9fc0216760909c4046ba09745.tar.gz u-boot-imx-dd620b26332eb1e9fc0216760909c4046ba09745.tar.bz2 | |
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
powerpc/8xxx: Remove dependency on <usb.h>
powerpc/85xx: enable USB2 gadget mode for corenet ds board
powerpc/85xx: verify the device tree before booting Linux
MPC8xxx: drop redundant boot messages
powerpc/85xx: Fix build failure for P1023RDS
powerpc/p2041rdb: Enable SATA support
powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500
powerpc/85xx: Fix up clock_freq property in CAN node of dts
85xx: enable FDT support for STX SSA board
powerpc/85xx: provide 85xx flush_icache for cmd_cache
powerpc/p2041rdb: Enable backside L2 cache support
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
powerpc/85xx: Add support for P2041[e] XAUI in SERDES
powerpc/85xx: Rename P2040 id & SERDES to P2041
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access
powerpc/85xx: Fix setting of EPAPR_MAGIC value
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/start.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 626ccce..878a3d6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -676,6 +676,8 @@ mck_return: /* Cache functions. */ +.globl flush_icache +flush_icache: .globl invalidate_icache invalidate_icache: mfspr r0,L1CSR1 |