diff options
| author | Aneesh Bansal <aneesh.bansal@freescale.com> | 2014-03-18 23:40:26 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:46 -0700 |
| commit | fb4a2409b46c98672557bb07dec8e873bef1e23c (patch) | |
| tree | 776fe2f1a2b4f98dc0ae9cc8186ccaeabda3f72d /arch/powerpc/cpu/mpc85xx/start.S | |
| parent | bea3cbb07fb4c47c2a0324a22bb83c020769f151 (diff) | |
| download | u-boot-imx-fb4a2409b46c98672557bb07dec8e873bef1e23c.zip u-boot-imx-fb4a2409b46c98672557bb07dec8e873bef1e23c.tar.gz u-boot-imx-fb4a2409b46c98672557bb07dec8e873bef1e23c.tar.bz2 | |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/start.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9eee549..9a7881f 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -122,7 +122,8 @@ _start_e500: #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ + !defined(CONFIG_E6500) /* ISBC uses L2 as stack. * Disable L2 cache here so that u-boot can enable it later * as part of it's normal flow |