diff options
| author | Wolfgang Denk <wd@denx.de> | 2011-04-05 12:24:20 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-04-05 12:24:20 +0200 |
| commit | 4db2fa7f9446d0f2fe8db3d62184b1212fe22707 (patch) | |
| tree | bc62cbfc14296551caebda626db7a90fef9ae844 /arch/powerpc/cpu/mpc85xx/speed.c | |
| parent | 75df0d594990875419121c6f8687472ac9f4ae7a (diff) | |
| parent | 7d3053fbf16caad4745f42f7ae3e38e9d3e964b5 (diff) | |
| download | u-boot-imx-4db2fa7f9446d0f2fe8db3d62184b1212fe22707.zip u-boot-imx-4db2fa7f9446d0f2fe8db3d62184b1212fe22707.tar.gz u-boot-imx-4db2fa7f9446d0f2fe8db3d62184b1212fe22707.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Conflicts:
drivers/usb/host/ehci-pci.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/speed.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 48 |
1 files changed, 37 insertions, 11 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f2aa8d0..e530494 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -107,25 +107,45 @@ void get_sys_info (sys_info_t * sysInfo) #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 #define FM2_CLK_SEL 0x20000000 +#define HWA_ASYNC_DIV 0x04000000 +#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) +#define HWA_CC_PLL 1 +#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) +#define HWA_CC_PLL 2 +#else +#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case +#endif rcw_tmp = in_be32(&gur->rcwsr[7]); #ifdef CONFIG_SYS_DPAA_PME - if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = freqCC_PLL[2] / 2; - else + if (rcw_tmp & PME_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqPME = sysInfo->freqSystemBus / 2; + } #endif #ifdef CONFIG_SYS_DPAA_FMAN - if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM1_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + } #if (CONFIG_SYS_NUM_FMAN) == 2 - if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM2_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + } #endif #endif @@ -162,7 +182,6 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif -#endif #ifdef CONFIG_QE qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) @@ -170,6 +189,12 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#ifdef CONFIG_SYS_DPAA_FMAN + sysInfo->freqFMan[0] = sysInfo->freqSystemBus; +#endif + +#endif /* CONFIG_FSL_CORENET */ + #if defined(CONFIG_FSL_LBC) #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ @@ -254,7 +279,8 @@ int get_clocks (void) gd->i2c2_clk = gd->i2c1_clk; #if defined(CONFIG_FSL_ESDHC) -#ifdef CONFIG_MPC8569 +#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ + defined(CONFIG_P1014) gd->sdhc_clk = gd->bus_clk; #else gd->sdhc_clk = gd->bus_clk / 2; |