diff options
| author | Timur Tabi <timur@freescale.com> | 2011-08-05 16:15:24 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-09-29 19:01:05 -0500 |
| commit | fbb9ecf7493fbd6b8c8af7d52e90c915459f7040 (patch) | |
| tree | b19bce4d9c77be58fc1aba43bd73625222c99f8f /arch/powerpc/cpu/mpc85xx/speed.c | |
| parent | 86df5142a14868ea0e24511f4293d43a611a2b39 (diff) | |
| download | u-boot-imx-fbb9ecf7493fbd6b8c8af7d52e90c915459f7040.zip u-boot-imx-fbb9ecf7493fbd6b8c8af7d52e90c915459f7040.tar.gz u-boot-imx-fbb9ecf7493fbd6b8c8af7d52e90c915459f7040.tar.bz2 | |
powerpc/mp: add support for discontiguous cores
Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more. We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/speed.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index a83dfeb..ce47532 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -41,6 +41,7 @@ void get_sys_info (sys_info_t * sysInfo) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); + unsigned int cpu; const u8 core_cplx_PLL[16] = { [ 0] = 0, /* CC1 PPL / 1 */ @@ -97,11 +98,11 @@ void get_sys_info (sys_info_t * sysInfo) freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i]; } rcw_tmp = in_be32(&gur->rcwsr[3]); - for (i = 0; i < cpu_numcores(); i++) { - u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf; + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel]; - sysInfo->freqProcessor[i] = + sysInfo->freqProcessor[cpu] = freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; } |