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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:08 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:15 -0500 |
| commit | 6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804 (patch) | |
| tree | 0fa435d86fef19ff6a83eedcc6c1c1f26527f8c5 /arch/powerpc/cpu/mpc85xx/speed.c | |
| parent | 69c7826759a69456df2a47fa4ef5dde19ab87e62 (diff) | |
| download | u-boot-imx-6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804.zip u-boot-imx-6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804.tar.gz u-boot-imx-6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804.tar.bz2 | |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.
Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/speed.c')
0 files changed, 0 insertions, 0 deletions