summaryrefslogtreecommitdiff
path: root/arch/powerpc/cpu/mpc85xx/release.S
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2010-05-05 22:35:27 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-07-26 13:07:57 -0500
commitfd3c9befa83eecf6e7c6ef03c501159fbf754143 (patch)
tree825bcfea93aea0ed8d270bd993262bab45982981 /arch/powerpc/cpu/mpc85xx/release.S
parent61054ffa1690b2aef4e845c6aa071840b93abff6 (diff)
downloadu-boot-imx-fd3c9befa83eecf6e7c6ef03c501159fbf754143.zip
u-boot-imx-fd3c9befa83eecf6e7c6ef03c501159fbf754143.tar.gz
u-boot-imx-fd3c9befa83eecf6e7c6ef03c501159fbf754143.tar.bz2
powerpc/p4080: Add workaround for erratum CPU22
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
-rw-r--r--arch/powerpc/cpu/mpc85xx/release.S6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 0b5b9da..53cefaf 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -136,6 +136,12 @@ __secondary_start_page:
mtspr L1CSR2,r8
#endif
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+ mfspr r8,L1CSR2
+ oris r8,r8,(L1CSR2_DCWS)@h
+ mtspr L1CSR2,r8
+#endif
+
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* Enable/invalidate the L2 cache */
msync