diff options
| author | York Sun <yorksun@freescale.com> | 2013-06-25 11:37:49 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:40 -0700 |
| commit | d217a9ad01ee6557a0c47cfc745eef6890507bbb (patch) | |
| tree | 7905c863e594930b7115b2e6d78a821f6205c79a /arch/powerpc/cpu/mpc85xx/release.S | |
| parent | c63e137014cf148bc1d234128941dccee3d519ae (diff) | |
| download | u-boot-imx-d217a9ad01ee6557a0c47cfc745eef6890507bbb.zip u-boot-imx-d217a9ad01ee6557a0c47cfc745eef6890507bbb.tar.gz u-boot-imx-d217a9ad01ee6557a0c47cfc745eef6890507bbb.tar.bz2 | |
powerpc/mpc85xx: Workaround for A-005812
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 15bbbc1..c15e83b 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -226,6 +226,21 @@ __secondary_start_page: 2: #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + /* + * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in + * write shadow mode. This code should run after other code setting + * DCWS. + */ + mfspr r3,L1CSR2 + andis. r3,r3,(L1CSR2_DCWS)@h + beq 1f + mfspr r3, SPRN_HDBCR0 + oris r3, r3, 0x8000 + mtspr SPRN_HDBCR0, r3 +1: +#endif + #ifdef CONFIG_BACKSIDE_L2_CACHE /* skip L2 setup on P2040/P2040E as they have no L2 */ mfspr r3,SPRN_SVR |