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| author | York Sun <yorksun@freescale.com> | 2012-05-07 07:26:47 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-07-06 17:30:33 -0500 |
| commit | 5e23ab0a31f19f894fe46bfab6f68b8bcfa10cf6 (patch) | |
| tree | 48f508182cde09a202b6464599925a5415f2fed8 /arch/powerpc/cpu/mpc85xx/release.S | |
| parent | 48f6a5c348453fc3ab33aaa91e5e4198a28678ff (diff) | |
| download | u-boot-imx-5e23ab0a31f19f894fe46bfab6f68b8bcfa10cf6.zip u-boot-imx-5e23ab0a31f19f894fe46bfab6f68b8bcfa10cf6.tar.gz u-boot-imx-5e23ab0a31f19f894fe46bfab6f68b8bcfa10cf6.tar.bz2 | |
powerpc/mpc85xx: Workaround for erratum CPU_A011
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index fe3b6d6..36c79d3 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -143,17 +143,29 @@ __secondary_start_page: mtspr L1CSR2,r8 #endif -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) - /* apply to P4080 rev 1 and rev 2 */ +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + */ mfspr r3,SPRN_SVR + rlwinm r6,r3,24,~0x800 /* clear E bit */ + + lis r5,SVR_P4080@h + ori r5,r5,SVR_P4080@l + cmpw r6,r5 + bne 1f + rlwinm r3,r3,0,0xf0 - li r4,0x30 - cmpw r3,r4 + li r5,0x30 + cmpw r3,r5 bge 2f - - mfspr r8,L1CSR2 - oris r8,r8,(L1CSR2_DCWS)@h - mtspr L1CSR2,r8 +1: + mfspr r3,L1CSR2 + oris r3,r3,(L1CSR2_DCWS)@h + mtspr L1CSR2,r3 2: #endif |