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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-03-19 03:40:08 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-07-26 13:07:56 -0500 |
| commit | 6aba33e939c41358cf731cbbdd9d5ca59c9266e8 (patch) | |
| tree | bb817fb19969dc9f7d90e0de0bc6c1a3496aba84 /arch/powerpc/cpu/mpc85xx/fdt.c | |
| parent | d51cc7a0cd1b9763a3250d44a07032f9b1bc96ae (diff) | |
| download | u-boot-imx-6aba33e939c41358cf731cbbdd9d5ca59c9266e8.zip u-boot-imx-6aba33e939c41358cf731cbbdd9d5ca59c9266e8.tar.gz u-boot-imx-6aba33e939c41358cf731cbbdd9d5ca59c9266e8.tar.bz2 | |
powerpc/p4080: Add support for CPC(Corenet platform cache) on CoreNet platforms
The CoreNet style platforms can have a L3 cache that fronts the memory
controllers. Enable that cache as well as add information into the
device tree about it.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/fdt.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 932466e..6c5fb36 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -28,6 +28,7 @@ #include <fdt_support.h> #include <asm/processor.h> #include <linux/ctype.h> +#include <asm/io.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif @@ -80,7 +81,30 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif +#ifdef CONFIG_SYS_FSL_CPC +static inline void ft_fixup_l3cache(void *blob, int off) +{ + u32 line_size, num_ways, size, num_sets; + cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; + u32 cfg0 = in_be32(&cpc->cpccfg0); + + size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; + num_ways = CPC_CFG0_NUM_WAYS(cfg0); + line_size = CPC_CFG0_LINE_SZ(cfg0); + num_sets = size / (line_size * num_ways); + + fdt_setprop(blob, off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, off, "cache-block-size", line_size); + fdt_setprop_cell(blob, off, "cache-size", size); + fdt_setprop_cell(blob, off, "cache-sets", num_sets); + fdt_setprop_cell(blob, off, "cache-level", 3); +#ifdef CONFIG_SYS_CACHE_STASHING + fdt_setprop_cell(blob, off, "cache-stash-id", 1); +#endif +} +#else #define ft_fixup_l3cache(x, y) +#endif #if defined(CONFIG_L2_CACHE) /* return size in kilobytes */ |