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authorWolfgang Denk <wd@denx.de>2010-08-03 22:45:13 +0200
committerWolfgang Denk <wd@denx.de>2010-08-03 22:45:13 +0200
commitac956293befb265b8958654d08c4ad52e605d46e (patch)
tree4fbfc08b1be8616bc5ee2032b53996ac0c5d64d8 /arch/powerpc/cpu/mpc85xx/fdt.c
parente9aecdec153ae166739858e6a570432449b979f7 (diff)
parent7385c28e9b5f7d47e6a8f1ad9800e6e70af714e2 (diff)
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Merge branch 'master' of /home/wd/git/u-boot/master
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/fdt.c')
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c24
1 files changed, 16 insertions, 8 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 2628cc5..932466e 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -298,17 +298,17 @@ void fdt_add_enet_stashing(void *fdt)
}
#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
-static void ft_fixup_clks(void *blob, const char *alias, unsigned long freq)
+static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
+ unsigned long freq)
{
- const char *path = fdt_get_alias(blob, alias);
-
- int off = fdt_path_offset(blob, path);
+ phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
+ int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
if (off >= 0) {
off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
if (off > 0)
printf("WARNING enable to set clock-frequency "
- "for %s: %s\n", alias, fdt_strerror(off));
+ "for %s: %s\n", compat, fdt_strerror(off));
}
}
@@ -317,14 +317,17 @@ static void ft_fixup_dpaa_clks(void *blob)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
- ft_fixup_clks(blob, "fman0", sysinfo.freqFMan[0]);
+ ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
+ sysinfo.freqFMan[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
- ft_fixup_clks(blob, "fman1", sysinfo.freqFMan[1]);
+ ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
+ sysinfo.freqFMan[1]);
#endif
#ifdef CONFIG_SYS_DPAA_PME
- ft_fixup_clks(blob, "pme", sysinfo.freqPME);
+ do_fixup_by_compat_u32(blob, "fsl,pme",
+ "clock-frequency", sysinfo.freqPME, 1);
#endif
}
#else
@@ -400,6 +403,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"clock-frequency", bd->bi_brgfreq, 1);
#endif
+#ifdef CONFIG_FSL_CORENET
+ do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
+ "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+#endif
+
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#ifdef CONFIG_MP