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authorYork Sun <yorksun@freescale.com>2013-06-25 11:37:41 -0700
committerYork Sun <yorksun@freescale.com>2013-08-09 12:41:38 -0700
commitcb93071bb6da21d17dd7d7d414a389b380f959b2 (patch)
treeef8cc19e0c01b00baeda237802d4b6b383d5e5f7 /arch/powerpc/cpu/mpc85xx/cpu_init.c
parent7adefb55adf3e55f3788c3b9682ba91d29da2595 (diff)
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mpc85xx: Base emulator support
Prepare for emulator support for mpc85xx parts. Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers. These two registers improve stability but not supported by emulator. Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c')
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 25beda2..1774462 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -532,8 +532,10 @@ skip_l2:
enable_cpc();
+#ifndef CONFIG_SYS_FSL_NO_SERDES
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0)) {