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| author | Wolfgang Denk <wd@denx.de> | 2011-01-25 21:13:04 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-01-25 21:13:04 +0100 |
| commit | 5aebe3b07254d9ec8f7ae23a4525a6c535a7f858 (patch) | |
| tree | 398660b7a43c39cee91c51e54678eab46aa7103d /arch/powerpc/cpu/mpc85xx/cpu.c | |
| parent | d6a5e6d531e357dd8016141f73d370d02886a7eb (diff) | |
| parent | 92966835e96af324fed574815036e481be807d04 (diff) | |
| download | u-boot-imx-5aebe3b07254d9ec8f7ae23a4525a6c535a7f858.zip u-boot-imx-5aebe3b07254d9ec8f7ae23a4525a6c535a7f858.tar.gz u-boot-imx-5aebe3b07254d9ec8f7ae23a4525a6c535a7f858.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 4ef9be1..1aad2ba 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2007-2010 Freescale Semiconductor, Inc. + * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -166,12 +166,14 @@ int checkcpu (void) } #endif +#if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } +#endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); @@ -284,7 +286,10 @@ void mpc85xx_reginfo(void) { print_tlbcam(); print_laws(); +#if defined(CONFIG_FSL_LBC) print_lbc_regs(); +#endif + } /* Common ddr init for non-corenet fsl 85xx platforms */ @@ -330,8 +335,10 @@ phys_size_t initdram(int board_type) ddr_enable_ecc(dram_size); #endif +#if defined(CONFIG_FSL_LBC) /* Some boards also have sdram on the lbc */ lbc_sdram_init(); +#endif puts("DDR: "); return dram_size; |