diff options
author | Allen Martin <amartin@nvidia.com> | 2012-12-19 13:02:36 -0800 |
---|---|---|
committer | Allen Martin <amartin@nvidia.com> | 2012-12-19 13:02:36 -0800 |
commit | a098cf41fdb2a6607c675f7fe4f3164617c9367e (patch) | |
tree | b37acb36f65909e6f74cc537d73efd883a1485a6 /arch/powerpc/cpu/mpc85xx/cmd_errata.c | |
parent | b8a7c467960ffb4d5a5e1eef5f7783fb6f594542 (diff) | |
parent | 095728803eedfce850a2f85828f79500cb09979e (diff) | |
download | u-boot-imx-a098cf41fdb2a6607c675f7fe4f3164617c9367e.zip u-boot-imx-a098cf41fdb2a6607c675f7fe4f3164617c9367e.tar.gz u-boot-imx-a098cf41fdb2a6607c675f7fe4f3164617c9367e.tar.bz2 |
Merge remote-tracking branch 'u-boot/master' into u-boot-arm-merged
Conflicts:
README
arch/arm/cpu/armv7/exynos/clock.c
board/samsung/universal_c210/universal.c
drivers/misc/Makefile
drivers/power/power_fsl.c
include/configs/mx35pdk.h
include/configs/mx53loco.h
include/configs/seaboard.h
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cmd_errata.c')
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 2be192d..e5ecf5d 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -24,6 +24,109 @@ #include <command.h> #include <linux/compiler.h> #include <asm/processor.h> +#include "fsl_corenet_serdes.h" + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004849 +/* + * This work-around is implemented in PBI, so just check to see if the + * work-around was actually applied. To do this, we check for specific data + * at specific addresses in DCSR. + * + * Array offsets[] contains a list of offsets within DCSR. According to the + * erratum document, the value at each offset should be 2. + */ +static void check_erratum_a4849(uint32_t svr) +{ + void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; + unsigned int i; + +#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) + static const uint8_t offsets[] = { + 0x50, 0x54, 0x58, 0x90, 0x94, 0x98 + }; +#endif +#ifdef CONFIG_PPC_P4080 + static const uint8_t offsets[] = { + 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac + }; +#endif + uint32_t x108; /* The value that should be at offset 0x108 */ + + for (i = 0; i < ARRAY_SIZE(offsets); i++) { + if (in_be32(dcsr + offsets[i]) != 2) { + printf("Work-around for Erratum A004849 is not enabled\n"); + return; + } + } + +#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) + x108 = 0x12; +#endif + +#ifdef CONFIG_PPC_P4080 + /* + * For P4080, the erratum document says that the value at offset 0x108 + * should be 0x12 on rev2, or 0x1c on rev3. + */ + if (SVR_MAJ(svr) == 2) + x108 = 0x12; + if (SVR_MAJ(svr) == 3) + x108 = 0x1c; +#endif + + if (in_be32(dcsr + 0x108) != x108) { + printf("Work-around for Erratum A004849 is not enabled\n"); + return; + } + + /* Everything matches, so the erratum work-around was applied */ + + printf("Work-around for Erratum A004849 enabled\n"); +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004580 +/* + * This work-around is implemented in PBI, so just check to see if the + * work-around was actually applied. To do this, we check for specific data + * at specific addresses in the SerDes register block. + * + * The work-around says that for each SerDes lane, write BnTTLCRy0 = + * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000. + + */ +static void check_erratum_a4580(uint32_t svr) +{ + const serdes_corenet_t __iomem *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + unsigned int lane; + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + if (serdes_lane_enabled(lane)) { + const struct serdes_lane __iomem *srds_lane = + &srds_regs->lane[serdes_get_lane_idx(lane)]; + + /* + * Verify that the values we were supposed to write in + * the PBI are actually there. Also, the lower 15 + * bits of res4[3] should be the same as the upper 15 + * bits of res4[1]. + */ + if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) || + (in_be32(&srds_lane->res4[1]) != 0x880000) || + (in_be32(&srds_lane->res4[3]) != 0x40000044)) { + printf("Work-around for Erratum A004580 is " + "not enabled\n"); + return; + } + } + } + + /* Everything matches, so the erratum work-around was applied */ + + printf("Work-around for Erratum A004580 enabled\n"); +} +#endif static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -137,6 +240,17 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 puts("Work-around for Erratum A004934 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004849 + /* This work-around is implemented in PBI, so just check for it */ + check_erratum_a4849(svr); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004580 + /* This work-around is implemented in PBI, so just check for it */ + check_erratum_a4580(svr); +#endif +#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 + puts("Work-around for Erratum PCIe-A003 enabled\n"); +#endif return 0; } |