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| author | Leo Liu <liucai.lfn@gmail.com> | 2011-01-19 19:50:47 +0800 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2011-02-05 17:01:52 -0600 |
| commit | 10fa8d7c703b564bcbdaa2345442e30483c01f98 (patch) | |
| tree | 064ca556baf861a0450960eed42bf51c050e394f /arch/powerpc/cpu/mpc83xx | |
| parent | f69b980d108b5f15ca7dd3f4284d5a66488c3625 (diff) | |
| download | u-boot-imx-10fa8d7c703b564bcbdaa2345442e30483c01f98.zip u-boot-imx-10fa8d7c703b564bcbdaa2345442e30483c01f98.tar.gz u-boot-imx-10fa8d7c703b564bcbdaa2345442e30483c01f98.tar.bz2 | |
mpc83xx: fix pcie configuration space read/write
This patch fix a problem for the pcie enumeration when the mpc83xx
pcie controller is connected with switch or we use both of the two
pcie controller.
Signed-off-by: Leo Liu <liucai.lfn@gmail.com>
fix codingstyle and compiler warning: 'pcie_priv' defined but not used
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc83xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc83xx/pcie.c | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 46a706d..52d4461 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -48,11 +48,26 @@ static struct { #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES +/* private structure for mpc83xx pcie hose */ +static struct mpc83xx_pcie_priv { + u8 index; +} pcie_priv[PCIE_MAX_BUSES] = { + { + /* pcie controller 1 */ + .index = 0, + }, + { + /* pcie controller 2 */ + .index = 1, + }, +}; + static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) { int bus = PCI_BUS(dev) - hose->first_busno; immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - pex83xx_t *pex = &immr->pciexp[bus]; + struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data; + pex83xx_t *pex = &immr->pciexp[pcie_priv->index]; struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); u32 dev_base = bus << 24 | devfn << 16; @@ -142,6 +157,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; + hose->priv_data = &pcie_priv[bus]; + pci_set_ops(hose, pcie_read_config_byte, pcie_read_config_word, |