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author | Simon Glass <sjg@chromium.org> | 2012-12-13 20:48:47 +0000 |
---|---|---|
committer | Tom Rini <trini@ti.com> | 2013-02-01 15:42:45 -0500 |
commit | c6731fe22ab1cc2f5c2b8be9b1db276d777f12c3 (patch) | |
tree | 00ac46c4d272af113b8abac3813f89ab985a57da /arch/powerpc/cpu/mpc83xx/pcie.c | |
parent | 748cd0591a9fe9eb23f20748bcb23035cd5ff517 (diff) | |
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ppc: Move mpc83xx clock fields to arch_global_data
Move al mpc83xx fields into arch_global_data and tidy up. Also indent
the nested #ifdef for clarity.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc83xx/pcie.c')
-rw-r--r-- | arch/powerpc/cpu/mpc83xx/pcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 52d4461..609b133 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -286,8 +286,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) get_clocks(); /* Configure the PCIE controller core clock ratio */ out_le32(hose_cfg_base + PEX_GCLK_RATIO, - (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16) - / 333); + (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk) + / 1000000) * 16) / 333); udelay(1000000); /* Do Type 1 bridge configuration */ |