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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:24 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:27 -0500 |
| commit | f31cfd19253713eea59311dec9e99df5d43b2db9 (patch) | |
| tree | 61e6f45481b4efa6949c5456fe81dcf0135480e6 /arch/powerpc/cpu/mpc5xxx/interrupts.c | |
| parent | 123922b1e583dc6bd6b8909af2d788f6e40a33a9 (diff) | |
| download | u-boot-imx-f31cfd19253713eea59311dec9e99df5d43b2db9.zip u-boot-imx-f31cfd19253713eea59311dec9e99df5d43b2db9.tar.gz u-boot-imx-f31cfd19253713eea59311dec9e99df5d43b2db9.tar.bz2 | |
powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT
When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc5xxx/interrupts.c')
0 files changed, 0 insertions, 0 deletions