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| author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-01-15 17:13:24 +0900 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-16 10:24:39 -0500 |
| commit | d928664f4101e24128c879956d1aa7c76509ea6a (patch) | |
| tree | 053f5991eb524a544cb9eeed765064388684f13a /arch/powerpc/cpu/74xx_7xx/kgdb.S | |
| parent | eb8b3f1edd405504febe6c9797750817b270f543 (diff) | |
| download | u-boot-imx-d928664f4101e24128c879956d1aa7c76509ea6a.zip u-boot-imx-d928664f4101e24128c879956d1aa7c76509ea6a.tar.gz u-boot-imx-d928664f4101e24128c879956d1aa7c76509ea6a.tar.bz2 | |
powerpc: 74xx_7xx: remove 74xx_7xx cpu support
All the 74xx_7xx boards are still non-generic boards:
P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Nye Liu <nyet@zumanetworks.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/74xx_7xx/kgdb.S')
| -rw-r--r-- | arch/powerpc/cpu/74xx_7xx/kgdb.S | 61 |
1 files changed, 0 insertions, 61 deletions
diff --git a/arch/powerpc/cpu/74xx_7xx/kgdb.S b/arch/powerpc/cpu/74xx_7xx/kgdb.S deleted file mode 100644 index 42b3a76..0000000 --- a/arch/powerpc/cpu/74xx_7xx/kgdb.S +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <command.h> -#include <74xx_7xx.h> -#include <version.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#if defined(CONFIG_CMD_KGDB) - - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - lis r3,0 - addis r4,r0,0x0040 -kgdb_flush_loop: - lwz r5,0(r3) - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - cmp 0,0,r3,r4 - bne kgdb_flush_loop - SYNC - mfspr r3,1008 - ori r3,r3,0x8800 - mtspr 1008,r3 - sync - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CONFIG_SYS_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CONFIG_SYS_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif |