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authorDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-01-09 17:32:50 +0100
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-01-16 21:06:46 +0100
commitf53830e74ede7c15740e13d9620dafb335c522ce (patch)
tree253d2714fca0ec2dabbfe22d29f050d804099a93 /arch/openrisc
parent0c7fd8f4660ed612db5d9e9343f77edfe5af090b (diff)
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MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT
Add Kconfig symbol for L1 cache shift like the kernel does. The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS. If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the cache sizes are automatically detected and ARCH_DMA_MINALIGN would be set to 128 Bytes. The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which corresponds to 32 Bytes. All current MIPS boards already used that value. While on it, fix the Malta board to use a value of 6 like the kernel port does. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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