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author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-01-09 17:32:50 +0100 |
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committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-01-16 21:06:46 +0100 |
commit | f53830e74ede7c15740e13d9620dafb335c522ce (patch) | |
tree | 253d2714fca0ec2dabbfe22d29f050d804099a93 /arch/openrisc | |
parent | 0c7fd8f4660ed612db5d9e9343f77edfe5af090b (diff) | |
download | u-boot-imx-f53830e74ede7c15740e13d9620dafb335c522ce.zip u-boot-imx-f53830e74ede7c15740e13d9620dafb335c522ce.tar.gz u-boot-imx-f53830e74ede7c15740e13d9620dafb335c522ce.tar.bz2 |
MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT
Add Kconfig symbol for L1 cache shift like the kernel does.
The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source
for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS.
If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the
cache sizes are automatically detected and ARCH_DMA_MINALIGN
would be set to 128 Bytes.
The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which
corresponds to 32 Bytes. All current MIPS boards already used
that value. While on it, fix the Malta board to use a value of 6
like the kernel port does.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/openrisc')
0 files changed, 0 insertions, 0 deletions