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authorStefan Roese <sr@denx.de>2014-11-16 12:47:00 +0100
committerMarek Vasut <marex@denx.de>2014-12-06 13:52:47 +0100
commit481549f8c1fa3a40729d0ff15c25380a043b6d41 (patch)
tree35fb86dea8c991d3a6c1ab32eb03ebb4d3e8815f /arch/openrisc
parentc877eaa8a04858c23ce7ebb82c59f7cf838545ef (diff)
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arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.h
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
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