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authorMinkyu Kang <mk7.kang@samsung.com>2010-04-19 10:26:18 +0900
committerMinkyu Kang <mk7.kang@samsung.com>2010-04-19 10:26:18 +0900
commit83653121d7382fccfe329cb732f77f116341ef1d (patch)
tree0b1ce6764252af15dfb2614372de98a44a7ec61f /arch/nios2/lib/cache.S
parent0f1f21a345e02a68ec16f7ab9e7dc687f9276089 (diff)
parent07739bcef5da07cc4a4edef8b91014ccc332eda3 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts: cpu/arm1176/cpu.c cpu/arm1176/start.S cpu/arm_cortexa8/s5pc1xx/Makefile cpu/arm_cortexa8/s5pc1xx/clock.c drivers/serial/serial_s5p.c include/asm-arm/arch-s5pc1xx/clk.h include/asm-arm/arch-s5pc1xx/gpio.h include/asm-arm/arch-s5pc1xx/uart.h Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/nios2/lib/cache.S')
-rw-r--r--arch/nios2/lib/cache.S74
1 files changed, 74 insertions, 0 deletions
diff --git a/arch/nios2/lib/cache.S b/arch/nios2/lib/cache.S
new file mode 100644
index 0000000..ee3b4b7
--- /dev/null
+++ b/arch/nios2/lib/cache.S
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+ .text
+
+ .global flush_dcache
+
+flush_dcache:
+ add r5, r5, r4
+ movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
+ ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
+0: flushd 0(r4)
+ add r4, r4, r8
+ bltu r4, r5, 0b
+ ret
+
+
+ .global flush_icache
+
+flush_icache:
+ add r5, r5, r4
+ movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE)
+ ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE)
+1: flushi r4
+ add r4, r4, r8
+ bltu r4, r5, 1b
+ ret
+
+ .global flush_cache
+
+flush_cache:
+ add r5, r5, r4
+ mov r9, r4
+ mov r10, r5
+
+ movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
+ ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
+0: flushd 0(r4)
+ add r4, r4, r8
+ bltu r4, r5, 0b
+
+ mov r4, r9
+ mov r5, r10
+ movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE)
+ ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE)
+1: flushi r4
+ add r4, r4, r8
+ bltu r4, r5, 1b
+
+ sync
+ flushp
+ ret