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authorken kuo <ken.kuoky@gmail.com>2013-06-08 11:14:09 +0800
committerMacpaul Lin <macpaul@gmail.com>2013-07-24 11:50:28 +0800
commit3c016704d9c5418479e68e4690759cb2be6f90d3 (patch)
tree420573e2d34c1f0c661e27d8f14d4a1cc75cef17 /arch/nds32/cpu
parentf6fd4140a5c7141a58a4e890951c9415be5347c4 (diff)
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nds32: Enable two banks of SDRAM on Andes board
The original adp-ag101/adp-ag101p initialize only one bank(64MB) by default at boot time, but it is not enough for some application, so increasing to two banks(128M). Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
Diffstat (limited to 'arch/nds32/cpu')
-rw-r--r--arch/nds32/cpu/n1213/ag101/lowlevel_init.S6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
index 29c93fe..55985cf 100644
--- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -38,6 +38,7 @@
#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
@@ -45,6 +46,7 @@
#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
+#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
/*
* parameters for the static memory controller
@@ -167,12 +169,12 @@ relo_base:
*/
led 0x1a
write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100
+ write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001140
/* clear empty BSR registers */
led 0x1b
li $r4, CONFIG_FTSDMC021_BASE
li $r5, 0x0
- swi $r5, [$r4 + FTSDMC021_BANK1_BSR]
swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
@@ -223,6 +225,8 @@ relo_base:
* - after remap: flash/rom 0x80000000, sdram: 0x00000000
*/
led 0x1c
+ write32 SDMC_B0_BSR_A, 0x00001000
+ write32 SDMC_B1_BSR_A, 0x00001040
setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
#endif /* #ifdef CONFIG_MEM_REMAP */