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| author | Macpaul Lin <macpaul@andestech.com> | 2011-09-23 17:31:27 +0800 |
|---|---|---|
| committer | Macpaul Lin <macpaul@gmail.com> | 2012-04-22 16:58:23 +0800 |
| commit | 1e52fea33ab3fadf459cc4919b32a136d4280d26 (patch) | |
| tree | 9dd386b193b6a43553ca25c2f031ed06957bfd55 /arch/nds32/cpu/n1213 | |
| parent | 2790bf69dc12fb9aeb9836904e5f57c7f83d5552 (diff) | |
| download | u-boot-imx-1e52fea33ab3fadf459cc4919b32a136d4280d26.zip u-boot-imx-1e52fea33ab3fadf459cc4919b32a136d4280d26.tar.gz u-boot-imx-1e52fea33ab3fadf459cc4919b32a136d4280d26.tar.bz2 | |
nds32/ag102: add header support of ag102 soc
Add device address offsets header of ag102 soc.
Add ag102 into mach-types.h.
Add asm-offsets.c for helping convert C headers into asm.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Diffstat (limited to 'arch/nds32/cpu/n1213')
| -rw-r--r-- | arch/nds32/cpu/n1213/ag102/asm-offsets.c | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/cpu/n1213/ag102/asm-offsets.c new file mode 100644 index 0000000..4769a95 --- /dev/null +++ b/arch/nds32/cpu/n1213/ag102/asm-offsets.c @@ -0,0 +1,54 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed to extract + * and format the required data. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <common.h> + +#include <linux/kbuild.h> + +int main(void) +{ +#ifdef CONFIG_FTSMC020 + OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); + OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); +#endif + BLANK(); +#ifdef CONFIG_FTAHBC020S + OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); + OFFSET(FTAHBC020S_CR, ftahbc02s, cr); +#endif + BLANK(); +#ifdef CONFIG_ANDES_PCU + OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */ +#endif + BLANK(); +#ifdef CONFIG_DWCDDR21MCTL + OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */ + OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */ + OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */ + OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */ + OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */ + OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */ + OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */ + OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */ + OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */ + OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */ + OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */ + OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */ + OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */ + OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */ + OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */ + OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */ + OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */ + OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */ + OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */ +#endif + return 0; +} |