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authorYao Cheng <saturdaycoder@gmail.com>2011-08-10 15:11:16 +0800
committerShinya Kuribayashi <skuribay@pobox.com>2011-09-03 10:43:45 +0900
commitdc344589ded4fb4d63ba7f0cdf670e2ffcf5e5a0 (patch)
treec75ea0e6061e2dd40ef82d4a131818e8e65b2621 /arch/mips
parenta1118d60423c1fe25afc9df9015f72739f96fd67 (diff)
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MIPS: mips32: fix wrong loop bound in flush_cache()
The issue is found when calling flush_cache() with zero "size" argument. The bound of loop is miscalculated in this case and flush_cache() enters a wrong flushing loop. Signed-off-by: Yao Cheng <saturdaycoder@gmail.com> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Sergei Shtylyov <sshtylyov@mvista.com> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/cpu/mips32/cpu.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 3ae397c..7b49e1b 100644
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -56,6 +56,10 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (size == 0)
+ return;
+
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
cache_op(Hit_Invalidate_I, addr);