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authorDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>2011-07-27 13:22:37 +0200
committerShinya Kuribayashi <skuribay@pobox.com>2011-07-31 23:26:41 +0900
commit7185adb48ef1e5b0f05263a7f791de340ddddeb2 (patch)
tree76406848852dcd399f1457c17471a110c23beb5e /arch/mips
parent60b74bde9280e85f4423c05a50ecc41de56ad980 (diff)
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MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG
This define is a board-specific config option and should be renamed to follow the U-Boot naming convention. Additionally, add an explaining comment for this option. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/cpu/mips32/start.S13
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 5d7467d..e829b02 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -64,9 +64,16 @@
_start:
RVECENT(reset,0) # U-boot entry point
RVECENT(reset,1) # software reboot
-#ifdef CONFIG_INCA_IP
- .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during
- .word 0x00000000 # booting phase of the flash
+#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
+ /*
+ * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
+ * access external NOR flashes. If the board boots from NOR flash the
+ * internal BootROM does a blind read at address 0xB0000010 to read the
+ * initial configuration for that EBU in order to access the flash
+ * device with correct parameters. This config option is board-specific.
+ */
+ .word CONFIG_SYS_XWAY_EBU_BOOTCFG
+ .word 0x00000000
#else
RVECENT(romReserved,2)
#endif