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authorGabor Juhos <juhosg@openwrt.org>2013-01-16 03:05:01 +0000
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2013-01-22 21:09:34 +0100
commit14fdd1a8bfd97de46042cda6086347b0d66461d4 (patch)
tree6fac1fbe6edbeef3aeda7e874b28ca30829118d6 /arch/mips
parent0ef48d4c89788056982772d32d6e97d2b6457abc (diff)
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MIPS: start{, 64}.S: fill branch delay slots with NOP instructions
The romReserved and romExcHandle handlers are accessed by a branch instruction however the delay slots of those instructions are not filled. Because the start.S uses the 'noreorder' directive, the assembler will not fill the delay slots either, and leads to the following assembly code: 0000056c <romReserved>: 56c: 1000ffff b 56c <romReserved> 00000570 <romExcHandle>: 570: 1000ffff b 570 <romExcHandle> In the resulting code, the second branch instruction is placed into the delay slot of the first branch instruction, which is not allowed on the MIPS architecture. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/cpu/mips32/start.S2
-rw-r--r--arch/mips/cpu/mips64/start.S1
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 9c1b2f7..22a9c1b 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -380,6 +380,8 @@ in_ram:
/* Exception handlers */
romReserved:
b romReserved
+ nop
romExcHandle:
b romExcHandle
+ nop
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index 2b8d531..bc7e41e 100644
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -259,3 +259,4 @@ in_ram:
/* Exception handlers */
romReserved:
b romReserved
+ nop