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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-01-24 06:27:55 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2013-01-27 16:40:15 +0100 |
| commit | 67d80c9f97f1b73d227f64efebf204221a611a70 (patch) | |
| tree | a6fa10d0f6eb01fa665a59ebda68366b68eaed82 /arch/mips | |
| parent | 248fe03f53772a61bb7355a4e45cd055dfdcf7b2 (diff) | |
| download | u-boot-imx-67d80c9f97f1b73d227f64efebf204221a611a70.zip u-boot-imx-67d80c9f97f1b73d227f64efebf204221a611a70.tar.gz u-boot-imx-67d80c9f97f1b73d227f64efebf204221a611a70.tar.bz2 | |
MIPS: start.S: don't save flush_cache parameters in advance
Saving the parameters in advance unnecessarily complicates
the code. The destination address is already saved in the
's2' register, and that register is not clobbered by the
copy loop. The size of the copied data can be computed
after the copy loop is done.
Change the code to compute the size parameter right
before calling flush_cache, and set the destination
address parameter in the delay slot of the actuall
call.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/cpu/mips32/start.S | 12 | ||||
| -rw-r--r-- | arch/mips/cpu/mips64/start.S | 12 |
2 files changed, 4 insertions, 20 deletions
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index d67dafa..77f1103 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -296,13 +296,6 @@ relocate_code: * t1 = target address * t2 = source end address */ - - /* - * Save destination address and size for later usage in flush_cache() - */ - move a0, t1 # a0 <-- destination addr - sub a1, t2, t0 # a1 <-- size - 1: lw t3, 0(t0) sw t3, 0(t1) @@ -311,11 +304,10 @@ relocate_code: addu t1, 4 /* If caches were enabled, we would have to flush them here. */ - - /* a0 & a1 are already set up for flush_cache(start, size) */ + sub a1, t1, s2 # a1 <-- size la t9, flush_cache jalr t9 - nop + move a0, s2 # a0 <-- destination address /* Jump to where we've relocated ourselves */ addi t0, s2, in_ram - _start diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S index d213c8e..80e6bb1 100644 --- a/arch/mips/cpu/mips64/start.S +++ b/arch/mips/cpu/mips64/start.S @@ -175,13 +175,6 @@ relocate_code: * t1 = target address * t2 = source end address */ - - /* - * Save destination address and size for dlater usage in flush_cache() - */ - move a0, t1 # a0 <-- destination addr - dsub a1, t2, t0 # a1 <-- size - 1: lw t3, 0(t0) sw t3, 0(t1) @@ -190,11 +183,10 @@ relocate_code: daddu t1, 4 /* If caches were enabled, we would have to flush them here. */ - - /* a0 & a1 are already set up for flush_cache(start, size) */ + dsub a1, t1, s2 # a1 <-- size dla t9, flush_cache jalr t9 - nop + move a0, s2 # a0 <-- destination address /* Jump to where we've relocated ourselves */ daddi t0, s2, in_ram - _start |