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| author | Wills Wang <wills.wang@live.com> | 2016-05-30 22:54:50 +0800 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-05-31 10:17:54 +0200 |
| commit | 375239174c6bc6a9966db333fa79f578154828f5 (patch) | |
| tree | 4c69c15d8e5ab0b4a1ac24535646a608ac3b6f75 /arch/mips/mach-ath79/ar933x | |
| parent | d58de3157e3d04ebbf8e928cff9bfc2b3be22ad7 (diff) | |
| download | u-boot-imx-375239174c6bc6a9966db333fa79f578154828f5.zip u-boot-imx-375239174c6bc6a9966db333fa79f578154828f5.tar.gz u-boot-imx-375239174c6bc6a9966db333fa79f578154828f5.tar.bz2 | |
mips: ath79: Rename get_bootstrap into ath79_get_bootstrap
Add a platform prefix for function name in order to make more readable,
and move it into ath79.h
Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/mips/mach-ath79/ar933x')
| -rw-r--r-- | arch/mips/mach-ath79/ar933x/clk.c | 4 | ||||
| -rw-r--r-- | arch/mips/mach-ath79/ar933x/ddr.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c index 9fcd496..6d98efc 100644 --- a/arch/mips/mach-ath79/ar933x/clk.c +++ b/arch/mips/mach-ath79/ar933x/clk.c @@ -9,7 +9,7 @@ #include <asm/addrspace.h> #include <asm/types.h> #include <mach/ar71xx_regs.h> -#include <mach/reset.h> +#include <mach/ath79.h> DECLARE_GLOBAL_DATA_PTR; @@ -17,7 +17,7 @@ static u32 ar933x_get_xtal(void) { u32 val; - val = get_bootstrap(); + val = ath79_get_bootstrap(); if (val & AR933X_BOOTSTRAP_REF_CLK_40) return 40000000; else diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c index 7f20d34..2a25e23 100644 --- a/arch/mips/mach-ath79/ar933x/ddr.c +++ b/arch/mips/mach-ath79/ar933x/ddr.c @@ -10,7 +10,7 @@ #include <asm/addrspace.h> #include <asm/types.h> #include <mach/ar71xx_regs.h> -#include <mach/reset.h> +#include <mach/ath79.h> DECLARE_GLOBAL_DATA_PTR; @@ -114,7 +114,7 @@ void ddr_init(void) writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); - val = get_bootstrap(); + val = ath79_get_bootstrap(); if (val & AR933X_BOOTSTRAP_DDR2) { /* AHB maximum timeout */ writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX); |