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| author | Paul Burton <paul.burton@imgtec.com> | 2016-05-27 14:28:05 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-05-31 09:44:24 +0200 |
| commit | 372286217f050bfd57695001d59f618c52822f40 (patch) | |
| tree | e2d926d936e6d65f2a229b19a347435f9f1d8d56 /arch/mips/lib | |
| parent | ace3be4f15875d74344336b9754c14274f940969 (diff) | |
| download | u-boot-imx-372286217f050bfd57695001d59f618c52822f40.zip u-boot-imx-372286217f050bfd57695001d59f618c52822f40.tar.gz u-boot-imx-372286217f050bfd57695001d59f618c52822f40.tar.bz2 | |
MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/lib')
| -rw-r--r-- | arch/mips/lib/cache.c | 22 | ||||
| -rw-r--r-- | arch/mips/lib/cache_init.S | 4 |
2 files changed, 9 insertions, 17 deletions
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index fbaafee..19a42ff 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -9,23 +9,13 @@ #include <asm/cacheops.h> #include <asm/mipsregs.h> -#ifndef CONFIG_SYS_CACHE_SIZE_AUTO - static inline unsigned long icache_line_size(void) { - return CONFIG_SYS_CACHELINE_SIZE; -} - -static inline unsigned long dcache_line_size(void) -{ - return CONFIG_SYS_CACHELINE_SIZE; -} + unsigned long conf1, il; -#else /* !CONFIG_SYS_CACHELINE_SIZE */ + if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO)) + return CONFIG_SYS_ICACHE_LINE_SIZE; -static inline unsigned long icache_line_size(void) -{ - unsigned long conf1, il; conf1 = read_c0_config1(); il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF; if (!il) @@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void) static inline unsigned long dcache_line_size(void) { unsigned long conf1, dl; + + if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO)) + return CONFIG_SYS_DCACHE_LINE_SIZE; + conf1 = read_c0_config1(); dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; if (!dl) @@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void) return 2 << dl; } -#endif /* !CONFIG_SYS_CACHELINE_SIZE */ - void flush_cache(ulong start_addr, ulong size) { unsigned long ilsize = icache_line_size(); diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 4bb9a17..bc8ab27 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -101,14 +101,14 @@ LEAF(mips_cache_reset) #ifndef CONFIG_SYS_CACHE_SIZE_AUTO li t2, CONFIG_SYS_ICACHE_SIZE - li t8, CONFIG_SYS_CACHELINE_SIZE + li t8, CONFIG_SYS_ICACHE_LINE_SIZE #else l1_info t2, t8, MIPS_CONF1_IA_SHF #endif #ifndef CONFIG_SYS_CACHE_SIZE_AUTO li t3, CONFIG_SYS_DCACHE_SIZE - li t9, CONFIG_SYS_CACHELINE_SIZE + li t9, CONFIG_SYS_DCACHE_LINE_SIZE #else l1_info t3, t9, MIPS_CONF1_DA_SHF #endif |